1. Field of the Invention
The present invention relates to a bipolar transistor and to a manufacturing method for a bipolar transistor, and more specifically to an inverted-structure bipolar transistor with improved high-frequency characteristics, in which the collector is positioned above the emitter, and a manufacturing method for this bipolar transistor.
2. Background of the Invention
Because a bipolar transistor, in contrast to a field-effect transistor (FET), has a structure in which current flows in a direction that is perpendicular with respect to a substrate, the amount of current that can be injected per effective element surface area is large. For this reason, in applications such as integrated circuits and microwave elements, bipolar transistors are particularly applicable because of their high current driving capability and high power density. In recent years, bipolar transistors having an emitter with a wide energy gap compared to that of the base, that is, hetero-junction bipolar transistors (hereinafter referred to as HBTs) have, along with field-effect transistors, come to be used in a variety of high-speed circuit elements and high-frequency elements. However, to apply characteristics such as those of an HBT at even high frequencies, it is necessary to improve the maximum oscillation frequency (fmax) which is a measure of the performance of an HBT. The value of fmax of an HBT can be approximated by the following equation.
fmax≈(fT/8xcfx80RBCBC)1/2xe2x80x83xe2x80x83(1)
In the above equation, RB is the base resistance, CBC is the base-collector capacitance, and fT is the common-emitter current gain cutoff frequency. When an element is operating at a sufficiently high current, this cutoff frequency fT can be approximated by the following equation.
fT≈1/2xcfx80[(RB+RC) CBC+TF]xe2x80x83xe2x80x83(2)
In the above equation, RE and RC are the emitter resistance and collector resistance, respectively, and TF is the travel time of minority carriers in the region formed by the combination of the neutral base layer and the collector depletion layer. In recent years, as a result of significant advances in achieving thin elements, reduced feature sizes and improved electrodeforming technologies, fT has almost reached a limit which is established by the characteristics of the semiconductor material. Because of this situation, in order to improve fmax to even further, it is effective, as seen from the relationship shown in Equation (1), to make RB and CBC as small as possible. In the usual HBT, however, because there is a tradeoff relationship between RB and CBC, it is not easy to make both of these values small. This will be explained in terms of the prior art, which is shown in FIG. 9.
In FIG. 9, the MBE (molecular beam epitaxy) method is used to grow, onto a semi-insulator GaAs substrate 1, a collector-contact layer 6 having a thickness of 500 nm made from an n-type GaAs with silicon added to a high concentration (3xc3x971016 cmxe2x88x923), a collector layer 5 having a thickness of 500 nm made of n-type GaAs having silicon added to a low concentration (5xc3x971016 cmxe2x88x923) , a base layer 4 having a thickness of 80 nm and made from p-type GaAs with beryllium added to a high concentration (4xc3x971019 cmxe2x88x923), an emitter layer 3 having a thickness of 250 nm made of n-type Al0.25Ga0.75As with silicon added to a medium concentration (5xc3x971017 cmxe2x88x923), and an emitter contact layer 2 having a thickness of 150 nm made of n-type GaAs with silicon added to a high concentration (3xc3x971018 cmxe2x88x923), these being formed in the above-noted sequence.
Next, after crystal growth, an emitter electrode 101 using an AuGe metal alloy is formed first, using lift off method. Next, photoresist that defines the emitter region is patterned, and dry etching is done using chlorine gas so as to etch the emitter contact layer 2, thereby exposing the base layer 4. Next, lift off method is used to provide a non-alloy type of base electrode 102, made from titan, platinum, and gold, after which wet etching using a phosphoric acid hydrogen peroxide water solution is done to etch to the collector layer 5, with lift off being done at the point at which the sub-collector layer 61 appears, so as to form a AuGe metallic alloy collector electrode 103.
Finally, deep ion implantation (with an implantation energy of 200 keV, and a dose amount of 5xc3x971012 cmxe2x88x922) is used to form an element separation region 90, thereby completing the formation of the element.
In an HBT such as illustrated in FIG. 9, to reduce parasitic external collector capacitance in the external region 13 of the element, it is necessary to reduce the dimensions of the element external region 13. However, if the dimensions of the element external region 13 are made extremely small, the contact surface area of the base electrode 102 is reduced, this leading to an increase in the base resistance. Thus, in an HBT structure such as shown in FIG. 9, in which the emitter is positioned over the collector, there is a tradeoff relationship that obtains between the base resistance and the collector capacitance, this acting to limit the value of fmax.
To solve the above-noted problem, an HBT has been proposed in which the positional relationship between the emitter and the collector is inverted. In the HBT shown in FIG. 10, the MBE (molecular beam epitaxy) method is used to grow, on a semi-insulator GaAs substrate 1, an emitter-contact layer 2 having a thickness of 500 nm made from an n-type GaAs with silicon added to a high concentration (3xc3x971010 cmxe2x88x923), an emitter layer 3 having a thickness of 250 nm made of n-type Al0.25Ga0.75As with silicon added to a medium concentration (5xc3x971017 cmxe2x88x923) , a base layer 4 having a thickness of 80 nm and made from p-type GaAs with beryllium added to a high concentration (4xc3x971019 cmxe2x88x923) , a collector layer 5 having a thickness of 500 nm made of n-type GaAs having silicon added to a low concentration (5xc3x971016 cmxe2x88x923) , and a collector contact layer 6 having a thickness of 50 nm made of n-type GaAs with silicon added to a high concentration (3xc3x971018 cmxe2x88x923), these being formed in the above-noted sequence.
As can be seen from the drawings, because the collector capacitance only occurs in the element intrinsic region 12, compared with the bipolar transistor shown in FIG. 9, in which the emitter is on top, it is possible to greatly reduce the collector capacitance. In an HBT having this type of inverted structure, however, the injection path of minority carriers from the emitter layer 3 to the base layer 4 (in this prior art example, because of the npn junction transistor, the electrons in the p-type base layer corresponding to minority carriers) is not only the path in the intrinsic region 12 (shown as the position 25b in the drawing), but also the path in the external region 13 (shown as the position 25a in the drawing).
While part of the minority carriers that are injected via the former path are lost through recombinations occurring at the junction boundary between the base layer 4 and the emitter layer 5 or within the base layer 4, a large number flow toward the collector layer 5. Almost all of the minority carriers that are injected via the later path recombine with pseudo-minority carriers (in this prior art example, because of the npn junction, these being positive holes) supplied from the base electrode 102, so that they do not contribute to current-amplitude effect of the transistor. Therefore, the proportion of minority carriers injected into the base layer 4 from the emitter layer 3 that are reclaimed in the collector layer 5 is much smaller than 1, and as a result there is a significant deterioration of the current gain. Thus, whether it is possible to achieve a high-performance inverted structure HBT depends on how effectively the minority carrier injection 25a in the element external region 13 can be suppressed.
In view of the above-noted problem with regard to an inverted HBT structure, Kroemer has proposed an element structure that suppresses minority carrier injection in the element external region (page 30, Vol. 70, Proceedings of IEE, 1982). FIG. 11 is a cross-sectional view of a prior art inverted structure HBT that recreates the basic concept of Kroemer While manufacturing method of the transistor in FIG. 11 is basically the same as for an HBT having a structure such as shown in FIG. 10, a feature of this element is the implantation of a p-type impurity (for example, Mg or Be) into the element external region 13, from the base layer 4 to the emitter layer 3, part of the emitter layer 3 being thereby changed from an n-type semiconductor to a p-type semiconductor so as to form an ion-implanted external base layer 43. After the ion implantation, to activate the p-type impurity, lamp annealing is usually done over a short period of time (at approximately 850xc2x0C.). Because the p-n junction that is formed in the element external region 13 is a p-n junction of the same Al0.25Ga0.75As materials, the threshold emitter voltage value (with respect to the base) at which minority carrier injection occurs is established by the energy band gap of the Al0.25Ga0.75As, this being approximately 1.7 volts. In the case of the p-n junction that is formed between the base and the emitter in the element intrinsic region 12, the emitter voltage threshold value is established by the base layer 4, which is made of GaAs, which has a relatively small energy band gap, this being approximately 1.4 volts. Because the emitter current is established as an exponential function of the emitter voltage, a very small change in the current threshold value that occurs between the element external region 13 and the element intrinsic region 12, given the same emitter voltage condition, leads to a suppression of minority carrier injection in the element external region 13, thereby achieving a degree of effectiveness.
In the prior art example that is shown in FIG. 12, ion implantation of hydrogen, boron, or oxygen or the like is done into the emitter layer 3 of the element external region 13, so as to form a semi-insulator region 91. This method, by making de-activating the emitter layer 3 of the element external region 13, prevents the injection of unwanted minority carriers in this region, and also has the feature that it does not require high-temperature processing.
In the prior art example that is shown in FIG. 11, however, because high-temperature heat treating is required in order to activate the p-type impurity that is ion injected, the impurities in each of the semiconductor layers in the element intrinsic region disperse, thereby resulting in a great change in the distribution of impurities. In the prior art as shown in FIG. 12, while high-temperature processing is not required, if the ion implantation dose amount is high enough to change the emitter layer 3 of the element external region 13 into a semi-insulator, the damage to the base layer 4 through which the ions pass becomes great. The damage to the base layer 4 leads to a lowering of the mobility and concentration of carriers in the base layer, this causing an increase in the sheet resistance of the base layer 4 and the contact resistance of the base electrode 102. If the dose amount is lower to a level at which damage to the base layer 4 is suppressed, there is the problem of not being able to sufficiently reduce injecting minority carriers in the element external region 13.
Accordingly, an object of the present invention is to improve over the above-noted drawbacks in the prior art, by providing a high-performance bipolar transistor which suppresses the injection of parasitic minority carriers in the element external region, and by providing a method of manufacturing the above-noted bipolar transistor.
In order to achieve the above-noted objects, the present invention adopts the following basic technical constitution.
Specifically, a first aspect of a bipolar transistor according to the present invention is a bipolar transistor which has an emitter contact layer formed on a semiconductor substrate, an emitter layer formed onto said emitter contact layer, a base layer that serves as the transistor region and an external base layer that serves as a base extension part formed over the emitter layer, and a collector layer that is formed onto said base region, said layers being formed in this sequence, wherein said bipolar transistor being provided with a buffer emitter layer in said emitter layer of a transistor region that makes contact with said base layer, thereby the effective energy barrier of minority carriers that are injected from said emitter layer into said base layer is lowered, and the energy barrier of minority carriers that are injected from said emitter layer into said external base region is increased without providing said buffer emitter layer in said transistor external region that is adjacent to said transistor region.
In a second aspect of the above-noted bipolar transistor, the energy band gap of the above-noted buffer emitter layer becomes smaller than the energy band gap of the emitter layer as the distance to the base layer becomes smaller.
In a third aspect of the above-noted bipolar transistor, the energy band gap of the above-noted buffer emitter layer is the same as the energy band gap of the base layer.
In a fourth aspect of the above-noted bipolar transistor, the energy band gap of the above-noted buffer emitter layer is a width that is between the energy band gap of the base layer and the energy band gap of the external base layer.
In a fifth aspect of the above-noted bipolar transistor, the energy band gap of the above-noted base layer is smaller than the energy band gap of the external base layer.
In a sixth aspect of the above-noted bipolar transistor, the impurity concentration in the buffer emitter layer is higher than the impurity concentration in the emitter layer.
A method of manufacturing a bipolar transistor according to the present invention, is a method of manufacturing a bipolar transistor which has an emitter contact layer, an emitter layer, a base layer, and a collector layer that are formed in this sequence onto a semiconductor layer, wherein the part of the emitter layer that makes contact with the base layer being provided with a buffer emitter layer so that the energy barrier of minority carriers injected into the base layer is effectively reduced, this manufacturing method having a step of removing the above-noted collector layer, base layer, and buffer emitter layer in the transistor external region, so as to form an external base layer on the surface of the emitter layer.
In a second aspect of the above-noted method of manufacturing a bipolar transistor, the energy band gap of the above-noted buffer emitter layer is made smaller than the energy band gap of the emitter layer as the distance to said base layer becomes smaller.
In a third aspect of the above-noted method of manufacturing a bipolar transistor, the energy band gap of the above-noted buffer emitter layer is made the same as the energy band gap of the base layer.
In a fourth aspect of the above-noted method of manufacturing a bipolar transistor, the energy band gap of the above-noted buffer emitter layer is made a width that is between the energy band gap of the base layer and the energy band gap of the external base layer.
In a fifth aspect of the above-noted method of manufacturing a bipolar transistor, the energy band gap of the above-noted base layer is made smaller than the energy band gap of the external base layer.
In a sixth aspect of the above-noted method of manufacturing a bipolar transistor, the impurity concentration in the buffer emitter layer is made higher than the impurity concentration in the emitter layer.
A bipolar transistor according to the present invention is one in which an emitter contact layer is formed on a semiconductor substrate, an emitter layer being formed over this emitter contact layer, a base layer that serves as the transistor region and an external base layer that serves as a base extension part being formed over the emitter layer, and a collector layer being then formed over the base layer, in the sequence indicated herein. In this bipolar transistor, a composition gradient buffer emitter layer that forms part of the emitter layer between the emitter layer of the transistor region and the base layer is provided, the configuration being made such that the conductive band on the junction boundary surface between the emitter layer and the base layer is continuous, the conductive band on the junction boundary surface between the emitter layer and the external base layer being non-continuous, so that, without providing the above-noted composition gradient layer in the base extension part that is adjacent to the transistor region, the emitter is formed by the emitter layer and the composition gradient layer, the result being that the potential barrier of minority carriers in the transistor region is lowered and the flow of injected minority carriers from the emitter layer into the base layer is made smoothly. Additionally, by removing the composition gradient layer that acts to reduce the potential barrier in the element external region, the injection of parasitic minority carriers from the emitter layer into the external base layer is suppressed, thereby resulting in a high-performance inverted-structure bipolar transistor.